This invention generally relates to a method and apparatus for refreshing Dynamic Random Access Memory (DRAM) cells. Particularly, the invention relates to a method and apparatus for saving power during an auto-refresh operation.
System designers continually push integrated circuit (IC) manufacturers to design ICs, such as volatile-memory ICs, having lower power requirements.
Because the data stored in a volatile memory cellxe2x80x94such as a dynamic-randomaccess-memory (DRAM) cellxe2x80x94degrades relatively quickly, the data must be periodically refreshed. Therefore, an IC that includes one or more volatile memory cells periodically implements refresh cycles in response to system auto-refresh commands.
During a typical refresh cycle, a sense amplifier reads the data stored in the memory cell and then writes the same data back into the cell. More specifically, the cell stores a signal level, such as a voltage level, that represents the value of the stored data. For example, a voltage level of Vcc often represents a data value of logic 1, and a voltage level of ground (0 V) often represents a data value of logic 0. Unfortunately, well-known phenomena such as memory-cell leakage cause this signal level to decay over time. If this signal level is not maintained, it may decay to a point where it represents a data value different than the data value originally stored in the memory cell. For example, a voltage level of Vcc (logic 1) may decay toward 0 V (logic 0), and if not maintained, may eventually become close enough to 0 V to represent logic 0 instead of logic 1. To maintain the stored signal level, the IC containing the DRAM cell implements a refresh cycle during which the sense amplifier receives the signal level from the cell, and restores the signal level of the cell to its full value (i.e., Vcc for logic 1 and 0 V for logic 0).
During normal operation of an IC that contains a volatile memory cell, the memory device incorporating the cell periodically issues an auto-refresh command to refresh the cell in response to a system auto-refresh command. For example, the memory device may include multiple rows of memory cells and a refresh address counter that indicates the row to be refreshed. Each auto-refresh command causes the IC to implement a respective auto-refresh cycle during which the IC refreshes the cells in the addressed row and increments or decrements the counter by one. Subsequent auto-refresh commands repeat this operation, and when all of the rows have been refreshed, the counter xe2x80x9cturns overxe2x80x9d so that the IC can continue to refresh the rows.
To insure that the system issues auto-refresh commands frequently enough to prevent the memory cells from losing their respective data, the memory device manufacturer specifies the maximum time period that can elapse between successive refreshes of a memory cell. Furthermore, to insure that the refresh cycles are long enough to allow the IC to adequately refresh a memory cell, the memory manufacturer specifies the minimum duration for each refresh cycle. Therefore, once the memory device issues an auto-refresh command to a row of memory cells, a system containing the memory device must wait at least this minimum duration before a memory access command to the row of the memory device can be acted on.
Auto-refresh commands pre-charge the input and output lines, just as required in an activate command in preparation for a read or write operation. As a result, auto-refresh commands consume valuable power and resources from the system. What is needed is a DRAM which reduces the power consumption during an auto-refresh operation.
The present invention provides a DRAM device, and method for using same, capable of reducing power consumption in an auto-refresh mode. In one aspect, the invention provides a method for operating a complementary input/output line pair driver circuit in a first memory access mode of operation to enable the driver circuit to pre-charge the input/output lines to a first voltage, and operating the driver circuit during an auto refresh mode to prevent the driver circuit from pre-charging the input/output lines to the first voltage. As such, pre-charging of the input/outlines is not accomplished during an auto-refresh operation and power consumption is reduced.
In another aspect, a driver for a dynamic memory device is disclosed, comprising a pair of complementary input/output lines connectable to a memory array, and a control circuit responsive to at least first and second control signals. The first control signal causes the control circuit to apply a first voltage and a second voltage to the input/output lines during memory access operations, and the second control signal, applied during an auto refresh operation, causes the control circuit to prevent application of at least one of the first and second voltages to the input/output lines during an auto-refresh operation.
These and other aspects and advantages of the invention will be apparent from the following detailed description and accompanying drawings.